Arria II GX: Unconstrained clock in tranceiver reconfiguration block

Hi,

by fitting my design I get warnings like this:

Warning: Node: ...alt2gxb_reconfig_rhm_component|alt_cal:calibration|alt_cal_edge_detect:pd0_det|pd_negedge was determined to be a clock but was found without an associated clock assignment.

One reconfiguration block is connected to four instances of a tranceiver channel with different starting_channel_number. There is one pll in the design. The reference clock and the reconfiguration clock are generated by this pll.

I'm using Quartus II 9.0 SP2.

This is the content of the TimeQuest sdc file:

derive_pll_clocks -create_base_clocks

derive_clock_uncertainty

set_false_path -from [get_ports {ResetN}]

Do I have to add something to the sdc file?

Thank You!