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Altera_Forum
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15 years ago

Arria-ii global clock input

Hi!! I am using ARRIA-II FPGA EP2AGX125EF35I5N 1152 FBGA. I have interfaced DDR3 memory in Bank 7A. Thus this bank is assigned to VCCIO of 1.5V. This bank has GCLK Pins 5P, 5N. I want to prov...
Altera_Forum's avatar
Altera_Forum
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15 years ago

I believe LVDS will need a VCCIO of 2.5V, so running LVDS on those pins will not do.