New Contributor
Regular ContributorHi,
I think the first step is to check if the board connections were done as per the recommendations.
The VCCLSENSE and GNDLSENSE pins should be connected if required as per Table 9 in https://www.intel.com/content/www/us/en/programmable/documentation/wtw1404286459773.html#wtw1420544425270
The Pin Connection Guidelines (above link) also provides recommendation on all the other supply and GND pins.
Also refer the Power Delivery Network (PDN) tool https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_dev_specific_pdn_tool.pdf
There are couple of training videos available on how to do the Power analysis. Please go through below links:
https://www.youtube.com/watch?v=4S1A3rHhTio
https://www.youtube.com/watch?v=_xDWT1Omy7A
https://www.youtube.com/watch?v=5IMLMiBxIKE
Regards.
New ContributorYesterday I removed the connection between VCCLSENSE and the 1.8V power plane. The power consumed on 1.8V was still huge. Using the early power estimator:
0.9V (Vcc + Vccp + Vcceram): epe 524mA, measured 211mA
1.8V (Vcch_gxbl + Vccpt + Vccpgm + Vccbat + vcca_pll + vccio): epe 110mA (measured 461mA)
This is the static power with no clock, unconfigured device. I tried to configure the FPGA and
1- It works
2- The measured static power consumption tends to the theoretical values :
600mA@0.9V (epe 524mA)
151mA@1.8V (epe110mA)
This is still quite high on the 1.8V rail. The epe is computing the static power for a configured device. I did not found any information about the unconfigured power consumption, which looks to be very high on some power rails.
