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FvM's avatar
FvM
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1 year ago

Arria 10 Variable Precision DSP Blocks Floating Point Exception Handling

Hi, Arria 10 documents seem not to specify behaviour of DSP Blocks in floating point modes with infinity or NaN input. In contrast, Stratix 10 DSP exception behaviour is specified in detail in "Vari...
Fpga Devkit
FvM's avatar
FvM
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1 year ago

Hi,
you are referring to the difference between qNaN (quiet NaN) and NaN in Intel documents. In my view, this is just a clarification, not a difference. When FP user manual talks about NaN results, it should write qNaN, because qNaN (NaN with mantissa MSB, respectively bit 22 set) is the required response of illegal arithmetic operations according to IEEE 754.

See also: floating point - What is the difference between quiet NaN and signaling NaN? - Stack Overflow

I guess, most FPGA users don't know the difference between NaN codes, interestingly even ModelSim and QuestaSim are confusing the different NaN codes. They are displaying qNaN (bit 22 set) as "NAN" and sNaN (signalling NaN, bit 22 cleared) as "QNAN", I just tried out of curiosity. Reading Stratix DSP user manual strictly, it doesn't tell how sNaN input is propagated, but I assume that the hardware follows IEEE 754 also in this point and outputs qNaN (vulgo NaN).

I believe that the shown subtile differences are another reason why we should have an explicite specification of Arria 10 DSP block exception behaviour. For my part, the issue can be closed in expectation of a complete Arria 10 DSP block specification.

Best regards
Frank