Arria 10 Variable Precision DSP Blocks Floating Point Exception Handling

The DSP on Arria® 10 devices do not support denormal number input, it does not contain any exception flag signals.

And the notification: "If the input is a denormal value, the IP core forces the value to zero and treats the value as a zero before going through any operation." under Floating-Point IP Cores User Guide - 1.5. Floating-Point IP Cores General Features is suitable for the Arria 10 devices, because this document is included in the Intel® Arria® 10 FPGAs Support Collection.

Hi,
thanks for answering. I was specifically asking for propagation of NaN and +/-inf input to Arria FP DSP blocks. It's a valid assumption that hardware DSP implements the same behaviour as FP software IP, but in my view it's still a guess. The behaviour is clearly specified in respective DSP block user manual for other devices like Stratix 10, so why not for Arria 10?

I presume Intel support has more substantial sources to answer the question than conclusions.

Regards
Frank

Hi,

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The Floating-Point IP Cores are always implemented on the Variable Precision DSP Blocks. The description in Floating-Point IP says that the input not-a-number (NaN), infinity, zero, and normal numbers are supported, means when using the DSP blocks as a Floating-Point IP, these kind of inputs are supported. But other situations are not included, for example when implementing an Fixed-Point IP on DSP blocks.

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The Variable Precision DSP Blocks on Stratix® 10 device are not the same as Variable Precision DSP Blocks on Arria® 10 device, the Stratix® 10 device supports the exception handling features for the floating-point arithmetic , so the document Intel® Stratix® 10 Variable Precision DSP Blocks User Guide introduces this feature in detail. It describes the handling of the input Quiet Not A Number (qNaN) , and do not contain descriptions on the input NaN.

Thanks.

Best Regards,

Shuo Zhang

Hi,
you are referring to the difference between qNaN (quiet NaN) and NaN in Intel documents. In my view, this is just a clarification, not a difference. When FP user manual talks about NaN results, it should write qNaN, because qNaN (NaN with mantissa MSB, respectively bit 22 set) is the required response of illegal arithmetic operations according to IEEE 754.

See also: floating point - What is the difference between quiet NaN and signaling NaN? - Stack Overflow

I guess, most FPGA users don't know the difference between NaN codes, interestingly even ModelSim and QuestaSim are confusing the different NaN codes. They are displaying qNaN (bit 22 set) as "NAN" and sNaN (signalling NaN, bit 22 cleared) as "QNAN", I just tried out of curiosity. Reading Stratix DSP user manual strictly, it doesn't tell how sNaN input is propagated, but I assume that the hardware follows IEEE 754 also in this point and outputs qNaN (vulgo NaN).

I believe that the shown subtile differences are another reason why we should have an explicite specification of Arria 10 DSP block exception behaviour. For my part, the issue can be closed in expectation of a complete Arria 10 DSP block specification.

Best regards
Frank

Hi,

​

The point I want to clarify is not to figure out the difference between the qNaN and the NaN.

I mean that the description which includes the qNaN in the documentation Intel® Stratix® 10 Variable Precision DSP Blocks User Guide mainly talks about the Exception Handling feature. And this feature is not supported by the Arria® 10 device, so the part Variable Precision DSP Blocks in Arria® 10 Devices in documentation does not contain any information on this.

And the handling of the NaN or other special case numbers is described in the documentation Floating-Point IP Cores User Guide, this User Guide focus on the Floating-Point IP Cores, so the description in it is suitable for all the devices which can support the FP IPs, including the Arria® 10 devices.

Thanks.

Best Regards,

Shuo