JPrig
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New ContributorArria 10 TRX re-calibration during JTAG programming
Hi,
I debug a custom Arria 10 design where a receiver CDR does not manage to hold itself locked to data. I see that a stable free-running clock is required at CLKUSR and TX PLL before device power-...
Hi Julia,
Please refer this link: https://www.intel.com/content/www/us/en/programmable/documentation/nik1398707230472.html#lbg1490124002611
Pt#2:
The reconfiguration block performs the following steps:
- Sets the xcvr_mode signal of the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP core to the requested speed.
- Reads the generated .mif file for the configuration settings and configures the transceiver accordingly.
- Selects the corresponding transceiver PLL.
- Triggers the transceiver recalibration.
Regards.
- Sets the xcvr_mode signal of the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP core to the requested speed.
