Arria 10 sx layout instructions

Hi,

We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum case, did not reach us as intended. As a result, we have a backlog of cases that we are currently working through.

Please be assured that we are doing everything we can to resolve this as quickly as possible. This will take some time, and we appreciate your patience and understanding during this period of time. Thank you again for your patience and understanding, and we are committed to provide you with the best possible support.

The DDR4 layout guideline for Arria 10 device can be found in Arria 10 EMIF IP UG.

Link: https://www.intel.com/content/www/us/en/docs/programmable/683106/24-1-19-2-3/design-layout-guidelines-01.html

I think you already found that in this thread. https://community.intel.com/t5/Programmable-Devices/Arria10-to-DDR4-layout-guidelines/m-p/1625761#M97211

I'm not familiar with Serial Lite and I think it's better to submit another thread to ask your question about Serial Lite because of system issue last time.

I'm going to close this thread and continue the support on this thread https://community.intel.com/t5/Programmable-Devices/Arria10-to-DDR4-layout-guidelines/m-p/1625761#M97211.

Regards,

Adzim