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Altera_Forum's avatar
Altera_Forum
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9 years ago

Arria 10 SX - The Fitter cannot place logic IO_LANE ???

Hello, Actually, I use a Reflex CES Achilles board with a SoC FPGA Arria 10 (10AS066H4F34E3SG). The board is also equipped with two DDR4 memory (2x8 GB). One of them can be accessible from the ...
SYi's avatar
SYi
Icon for New Contributor rankNew Contributor
6 years ago

At the ReFLEX's Knowledge base, I found below answer.

[FW]-[Achilles]-[Clocks]- I/O conflicts with clocks

Posted by Olivier Thomann on 31 October 2018 05:26 PM

Issue description:

There can be a conflict between both DDR4 and clk_25mhz_fpga clocks in the design. Both inputs try to access the same I/O PLL.

You may have the following error with Quartus Prime Pro:

Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 IO_LANE(s)).

Resolution advise:

You can add a "Global Clock" constraint on clk_25mhz_fpga, even if it results to a non-optimal PLL placement:

set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk_25mhz_fpga