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Altera_Forum
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8 years ago

Arria 10 spine clock region overused

Hi, I'm trying to build a fimware with several transceiver banks. If I use 4 banks, it's fine. But 5 banks cause congestion in the "spine clock region" and the compilation sits in "IO Placeme...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

I managed to fix this by setting the clocks to non-global clock. Here's the constraint that did the trick. There must be one constraint like this per channel.

set_instance_assignment -name GLOBAL_SIGNAL OFF -to "LLI:lli_inst|GWT_6ch:\\multiLink_gen_loop:1:multiLink_gen_gwt:u0|GWT_6ch_GWT_BANK_10_up7bqka:gwt_bank_0|GWT_6ch_altera_xcvr_native_a10_161_pn5wopi:xcvr_native_a10_0|twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|out_pld_pcs_rx_clk_out"

Karol.