New Contributor
ContributorHi
The jitter requirements come from full band jitter value.
If you probe the PLL reference clock by oscilloscope the equipment will measure the full band jitter with Pk to Pk and RMS parameters.
New ContributorThank you for your reply
I know the jitter performance of my reference clock. I have a datasheet for it that states it clearly.
I am trying to understand what the requirements are to make sure that my reference clock is adequate.
Could you explain what are the jitter requirements for the reference clock? Where do these requirements come from? Are they written in some spec.?
Are the jitter requirements dependent on DDR4 data rate?
Regards,
ContributorHi
Jitter amount affects the timing margin in the IP. If the reference clock has more jitter than requirement there may be malfunction on the IP due to the timing issue. The jitter requirement is consistent regardless any DDR4 data rate.
New ContributorThanks,
For Arria 10 I use LVDS 133MHz as reference clock for the DDR4 controller with 0.37pSec typical RMS jitter (Integration over 0.1MHz-20MHz frequency band)
The spec for the Arria 10 as defined in Intel EMIF Arria® 10 FPGA IP User Guide, page 205 is 1.22ps at 1e-16 BER , Identifier: PHY_DDR4_REF_CLK_JITTER_PS.
Please advise if OK
tamir,
ContributorHi
Your reference clock jitter should be no problem to the Arria10 reference clock jitter spec.
