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abuerkle's avatar
abuerkle
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3 years ago

Arria 10 SGMII CDR does not lock to data

Hi I adapted the SGMII reference design from Rocketboards to our own hardware based on a Arria 10 SX SoC (https://www.rocketboards.org/foswiki/Documentation/A10SGMIIRDUserManualLTS). I use a 100MH...
abuerkle's avatar
abuerkle
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3 years ago

Hi,

The problem with the CDR lock was solved by adding load capacitors to the crystal providing the reference clock for the SGMII PHY. Probably the frequency of the reference clock was slightly off. The remaining problem is that I see packets with a wrong CRC on the TX side. RX seems to work fine without any issues. I'm not sure if this is still caused by the reference clock.

The number of erroneous packets decrease when I increase the clock frequency of the 125MHz reference clock for the Arria 10 transceiver by a few ppm. But with +40ppm increased frequency, I again see the issue with the nonlocking CDR. According to documentation, the CDR should lock when the data frequency is in range +/- 1000ppm. Or is that setting different in the TSE MAC?

Thank you and best regards,

Andreas