New Contributor
ContributorHi Andreas
1) Signaltap the PHY rx_is_lockedtoref signal, to see when rx_is_lockedtodata is low, whether the RX CDR still can lock to CDR reference clock or not. If rx_is_lockedtoref still can lock to CDR reference clock, then probably the data is missing somewhere.
2) Check if the actual frequency on the board and PHY match the IP parameters being set when generated.
3) Found below note regarding the 'Manual' option in Reset Controller on page 255 of A10 Transceiver PHY User Guide.
Try set the RX/TX digital reset mode to Manual.
"(2).a. If you are using the Transceiver PHY Reset Controller, you must configure the TX digital reset mode and RX digital reset mode to Manual to avoid resetting the Auto Speed Negotiation (ASN) block which handles the rate switch whenever the channel PCS is reset.
b. When the TX digitalreset is in Auto mode, the associated tx_digitalreset controller automatically resets whenever the pll_locked signal is deasserted. When in Manual mode, the associated tx_digitalreset controller is not reset when the pll_locked signal is deasserted, allowing the user to choose what to do.
c. When the RX digitalreset is in Auto mode, the associated rx_digitalreset controllerautomatically resets whenever the rx_is_lockedtodata signal is deasserted. When in Manual mode, the associated rx_digitalreset controller is not reset when the rx_is_lockedtodata signal is deasserted, allowing the user to choose what to do.
d. If the resets are configured to Auto mode for PIPE designs, then the digital reset will get asserted automatically when the lock signal is deasserted."
New ContributorHi, thank you for your support.
1) rx_is_lockedtoref is always '1' when rx_is_lockedtodata is '0'. When rx_is_lockedtodata is '1', rx_is_lockedtoref is toggling.
2) I measured the frequency at the reference clock input and it matches the 125MHz that are requested by the PCS.
3) Thank you for pointing to that. I guess that could be an issue once the CDR locks to the data.
While I measured the reference clock, I noticed that I don't get any RX data (100% packet loss instead of ~50%) when the oscilloscope probe is attached to the hardware. The rx_is_lockedtoref signal does not change, but it seems to have an impact on the received data.
I use an LVDS reference clock connected to a dedicated reference clock input pin. Do I need to configure an on-chip termination or is that enabled automatically?
What is required that the rx_is_lockedtodata is asserted? Is it depending on the transition of the input data?
Best regards,
Andreas
