New Contributor
ContributorHi Andreas
When rx_is_lockedtodata asserted this would indicates that the CDR PLL is locked to the incoming data rx_serial_data.
As I understood from the problem statement, you observed rx_is_lockedtodata and rx_digitalreset toggling periodically.
1) Does this issue occur when using Arria 10 SX SoC dev kit (in case you have used it), or this only occur in your own hardware?
To narrow down the scope of issue, the suggestion is to perform PHY serial loopback enabled to test the PCS and embedded PMA functions. This is to check if the PCS and embedded PMA could work correctly across multiple reset. To enable serial PHY loopback, set the loopback bit in the PCS control register to 1. //Refer Table 13. TX PMA Optional Ports
//https://www.intel.com/content/www/us/en/docs/programmable/683617/21-1/transceiver-phy-overview.html
See 4.2.9. PHY Loopback of TSE user guide
2) To verify if transceiver calibration was successful, monitor the rx_cal_busy & rx_cal_busy.
Calibration is complete when *_cal_busy is deasserted.
rx_cal_busy: When asserted, indicates RX channel is being calibrated.
tx_cal_busy: When asserted, indicates TX channel is being calibrated.
3) Please also check if your design has any timing violation.
4) Pls try enable 'Use separate TX/RX reset' in the Transceiver PHY Reset Controller IP. If not set, all channels will be reset once loss lock.
See Table 250. General Options of the Arria 10 Transceiver PHY User Guide for the definition.
https://www.intel.com/content/www/us/en/docs/programmable/683617/21-1/transceiver-phy-overview.html
New ContributorHi
1) Unfortunately, I haven't access to an Arria 10 SX SoC dev kit. When I enable loopback in the PCS, rx_is_lockedtodata remains asserted and the transceiver is not reset anymore.
2) rx_cal_busy and tx_cal_busy are both '0' and never change (checked with signaltap after programming).
3) No timing errors are reported by the Quartus timing analyzer. No unconstrained clock is reported. I was using the same constraints as in the Rocketboards design.
4) I observed no difference with separate reset enabled. I have a separate Transceiver PHY reset controller instance for each of the two SGMII channels. I guess this is only relevant if one instance is used for more than one channel.
Thank you for your help and best regards,
Andreas
