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Altera_Forum
Honored Contributor
Honored ContributorArria 10 reclk frequency limitations of fPLL
When instantiating an fPLL (in Qsys) with a reference clock frequency of 50 MHz the fitter reports the following error:
Error (15653): The Fitter cannot find a legal configuration for the follo...
Altera_ForumHonored Contributor
Honored ContributorThis is a known bug (https://www.altera.com/support/support-resources/knowledge-base/solutions/fb371226.html): the reference frequency must be outside [49 MHz, 51.5 MHz].
Can I set the reference clock frequency parameter to 48 MHz when the actual frequency is 50 MHz?
