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Altera_Forum
Honored Contributor
8 years agoI found this quote in the Intel FPGA Integer Arithmetic IP Cores User Guide, 17.1:
"If multiple Intel FPGA Multiply Adder or ALTERA_MULT_ADD IP cores occur in a design, the functions are distributed to as many different DSP blocks as possible so that routing to these blocks is more flexible. Fewer multipliers per DSP block allow more routing choices into the block by minimizing paths to the rest of the device."