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TSchu3's avatar
TSchu3
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10 months ago

Arria 10 M20k block usage- More block with less memory bits?

Hello I have a design that fits on the Arria 10 GX dev board with chip 10AX11552F4sI1SG which has 2713 M20K blocks. The total memory bits for this design are 36,171,984, all 2713 blocks are used. ...
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sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
10 months ago

Are you saying on the original device you used *exactly* the number of M20K blocks available, 2713? That is quite a feat.

As for why it may need more now, it really depends on how you are implementing the RAM. It may not be able to be optimized exactly the same way it was on the original chip.

Showing some code might help.

TSchu3's avatar
TSchu3
Icon for Occasional Contributor rankOccasional Contributor
10 months ago

Yes I used exactly 2713 blocks. Its really not that difficult. It did not use all of the bits though.

The RAM is implemented in many many ways, from Fifos to instantiated Block RAM IP.
I am not seeing how the RAM would not be implemented in the same way on the new chip. It is just a smaller version of the same Arria 10. It has fewer M20K blocks, not different memory blocks (M10k for example); its not a different family (Cyclone, Stratix, etc.)
I am failing to see how optimization could cause it to need MORE memory blocks when I significantly reduced the required memory bits.

Thanks