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RPDM's avatar
RPDM
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

Arria 10 LVDS transmitter IP Core needs more documentation

The LVDS transmitter IP core has some strange parameter settings which aren't fully documented, and don't make much sense with the current documentation.

I'm using the IP core with an external PLL, so my inputs are tx_in, tx_out, ext_fclk, ext_loaden, ext_coreclock and pll_areset.

The PLL reference clock is 156.25MHz and the PLL is set to output 100MHz timings from this (for a 10x serializer running at 1Gbps).

The core itself makes sense to me and I understand how the thing works but there are parameter settings that aren't clear:

Firstly, you need to tell the IP core whether the 'TX core registers clock' input is tx_coreclock or inclock, despite the fact that it's actually ext_coreclock (since we have an 'external' PLL). So you'd assume that the selection wasn't necessary, but changing the option appears to affect the SDC timings that are generated.

Secondly, you have to tell the IP core the 'Desired inclock frequency' for the PLL that's feeding the LVDS serializer. Again, this makes no sense as the only clock inputs into the LVDS serializer are at 100MHz (bar the fclk) and therefore have no relation to that PLL reference clock - since the PLL is 'external' to the LVDS serializer.

As it stands, I cannot be sure that the IP core is running reliably as the documentation doesn't clarify what affect the above two parameters have on the logic.

Can anyone shed any light on this?

Thanks,

Richard

  • Rahul_S_Intel1's avatar
    Rahul_S_Intel1
    5 years ago

    Hi ,

    I understand the below pointer. I would try to change the documentation as per the below feed back. But as an expectation, I cannot guarantee you the changes

    Firstly, you need to tell the IP core whether the 'TX core registers clock' input is tx_coreclock or inclock, despite the fact that it's actually ext_coreclock (since we have an 'external' PLL). So you'd assume that the selection wasn't necessary, but changing the option appears to affect the SDC timings that are generated.

    Secondly, you have to tell the IP core the 'Desired inclock frequency' for the PLL that's feeding the LVDS serializer. Again, this makes no sense as the only clock inputs into the LVDS serializer are at 100MHz (bar the fclk) and therefore have no relation to that PLL reference clock - since the PLL is 'external' to the LVDS serializer.

6 Replies

  • SKane5's avatar
    SKane5
    Icon for New Contributor rankNew Contributor
    5 years ago

    Some of this is speculation but here's my take.

    For the first setting, my guess is that they're covering the case where you have a clock the same frequency as tx_coreclk and use it to drive your logic rather than the PLL output. For example, if you had a 100 MHz clock input, drove the LVDS PLL at 1 Gbps with that, and used the 100 MHz clock input in the FPGA fabric. I don't think I'd run it that way but it gives the option.

    For the second, I agree that in External PLL mode, the Desired inclock frequency should only matter if TX core registers clock is set to inclock. It might have been overlooked in the GUI to use the core registers setting to gray out the inclock frequency. We use external PLL mode, set the TX core registers setting to tx_coreclock and desired inclock frequency to the PLL input frequency, and haven't had any problems.

  • migry_tech's avatar
    migry_tech
    Icon for New Contributor rankNew Contributor
    5 years ago

    As a general comment, Personally I find the Altera/Intel documentation hard going. It would really help if there were some more block diagrams. I recently used the ALTLVDS on the Cyclone II. The circuit didn't work. Finally I got it working by reversing the data inputs. The code was ported from a competitors FPGA. I read the ALTLVDS documentation several times, there are lots of words, but at least for me a lack of clarity and lack of nice block diagrams.

  • Rahul_S_Intel1's avatar
    Rahul_S_Intel1
    Icon for Frequent Contributor rankFrequent Contributor
    5 years ago

    Hi Richard,

    May I know still you need clarification , kindly let me know.

    • RPDM's avatar
      RPDM
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      I've got the core working, so I don't need help - but the documentation certainly needs many clarifications & the IP Core tool needs a few fixes. See my original post.

  • Rahul_S_Intel1's avatar
    Rahul_S_Intel1
    Icon for Frequent Contributor rankFrequent Contributor
    5 years ago

    Hi ,

    I understand the below pointer. I would try to change the documentation as per the below feed back. But as an expectation, I cannot guarantee you the changes

    Firstly, you need to tell the IP core whether the 'TX core registers clock' input is tx_coreclock or inclock, despite the fact that it's actually ext_coreclock (since we have an 'external' PLL). So you'd assume that the selection wasn't necessary, but changing the option appears to affect the SDC timings that are generated.

    Secondly, you have to tell the IP core the 'Desired inclock frequency' for the PLL that's feeding the LVDS serializer. Again, this makes no sense as the only clock inputs into the LVDS serializer are at 100MHz (bar the fclk) and therefore have no relation to that PLL reference clock - since the PLL is 'external' to the LVDS serializer.

  • Rahul_S_Intel1's avatar
    Rahul_S_Intel1
    Icon for Frequent Contributor rankFrequent Contributor
    5 years ago

    With the above I am closing the case , sorry for the inconvenience and confusion caused to you , because of documentation.