Arria 10 LVDS transmitter IP Core needs more documentation

Hi ,

I understand the below pointer. I would try to change the documentation as per the below feed back. But as an expectation, I cannot guarantee you the changes

Firstly, you need to tell the IP core whether the 'TX core registers clock' input is tx_coreclock or inclock, despite the fact that it's actually ext_coreclock (since we have an 'external' PLL). So you'd assume that the selection wasn't necessary, but changing the option appears to affect the SDC timings that are generated.

Secondly, you have to tell the IP core the 'Desired inclock frequency' for the PLL that's feeding the LVDS serializer. Again, this makes no sense as the only clock inputs into the LVDS serializer are at 100MHz (bar the fclk) and therefore have no relation to that PLL reference clock - since the PLL is 'external' to the LVDS serializer.