mke
New Contributor
New ContributorArria 10 IOPLL not locking
Hello,
I have a problem with our Arria 10 based board: the IOPLLs are not locking. None of the IOPLLs work as expected, whatever we do.
The exact FPGA model we use is 10AX027E2F29E1HG. And in a...
Hi,
Pasting here the content of PCG related to RREF pins:
RREF_[T,B][L,R] Input Reference resistor for fPLL, IOPLL, and transceiver, specific to the top (T) side or bottom (B) side and left (L) side or right (R) side of the device. If any REFCLK pin or transceiver channel on one side (left or right) of the device or IOPLL is used, you must connect each RREF pin on that side of the device to its own individual 2kΩ resistor to GND. Otherwise, you can connect each RREF pin on that side of the device directly to GND. In the PCB layout, the trace from this pin to the resistor needs to be routed so that it avoids any aggressor signals. The description says that even if IOPLL is used, you should connect these pins to GND via 2K resistor.
Also suggest you to check the recommendations provided for VCCA_PLL in PCG.
Regards
