Forum Discussion

TomCarpenter's avatar
TomCarpenter
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Arria 10 HPS Bridge Lockup after Reset

I'm having an incredibly frustraiting issue with an Arria 10 HPS which is bordering on the bizarre. Short story: The processor boots and runs fine on first run, all peripherals in the FPGA can be...
Fpga Devkit
tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi


After comparing the connection made in the screenshot you shared I found that the h2f reset input to the HPS is different from the reset to the other IPs.

I would suggest if they are connected to the same reset source.

The error you are seeing could be due to the HPS and the FPGA fabric are not resetting at the same time.


The reset output of the h2f from the hps is connected together with the clock reset for the other IPs.

You could try taking a look how it is connected in our GSRD.

https://www.rocketboards.org/foswiki/Documentation/Arria10SoCGSRD


Regards

Jingyang, Teh