Forum Discussion

MehmetFide's avatar
MehmetFide
Icon for New Contributor rankNew Contributor
3 years ago

Arria 10 GX: 64 bit atomic access to Avalon Bus through PCIe?

Hi, We have an external processor Arm Cortex A53 with Linux 5.4 aarch64 connected to an Altera Arria 10 GX FPGA through a PCIe bus. On the FPGA side, we have an Avalon bus, all addresses are se...
MehmetFide's avatar
MehmetFide
Icon for New Contributor rankNew Contributor
3 years ago

Hi @Wincent_Altera,

As you suggested, we have tested it with both internal RAM and external DDR ram without DMA.

The problem exists at both conditions. To be more specific, accessing bars as 8/16/32 bit data work fine. But 64 bit accesses (especially read attempt) corrupts the PCIe config page in the FPGA and it fully stops functioning. It only recovers when we reconfigure the FPGA.

My question is that anyone on Intel ever tested the PCIe hard core in the Arria 10 GX to do 64 bit data access?

Thank you.

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,

    I check previous record, we had tested and it able to run.
    I lay down some suggestion so that we can narrow down this further.

    The issue might be caused by data packing limitation in interconnect on AXI/Avalon boundary. If your AXI is 32bit wide and PCIe Avalon interface is 64bit wide. In such situation multiple two 32bit transactions will be used to implement 64bit transfer.

    If you want to further analyze, Singal TAP traces showing transactions on PCIe Avalon interface and HPS AXI should show what is going on.

    Please try

    1. can you please try disabling the "Enable Reordering" option (under the Controller tab)?
    2. At the same time, please try running the Calibrate Termination command in the EMIF Toolkit (Tools menu -> System Debugging Tools -> External Memory Interface Toolkit) to verify the optimal ODT settings.

    Regards,

    Wincent_Intel