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LFrin's avatar
LFrin
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
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Arria 10: Booting U-Boot from SD-Card does not configure FPGA

Hello,

I have adapted the example for the Arria 10 SOCDK (Arria 10 SoC - Boot from SD Card) to the HAN-Pilot-Platform evaluation board from Terasic. I used the make_sdimage_p3.py script to generate the SD-Card image without linux binaries:

Partition 3: (format raw, type 0xA2) - u-boot-splx4.sfp
Partition 1: (format fat) - sdfs folder with - fit_spl_fpga.itb and u-boot.img
Partition 2: (format ext3) - empty

The SOC start-up seems to be ok, but the FPGA does not get configured:

Boot Console Arria 10 SOC

When i start the board without SD-Card, put it in, and then connect with the debugger and start the system with the Debugging U-Boot script. The system boots and the FPGA gets configured…

The start-up runs like from SD-Card, but the FPGA gets configured!

Some more informations:

  1. Quartus (22.3 Pro) compilation with “Early Release of HPS IO”
    1.1 Qsys EMIF with enabled “Early Release Mode”

  2. Convert .sof to .rbf with: quartus_cpf.exe --convert --hps -o bitstream_compression=off golden_top.sof golden_top.rbf

  3. Make fit_fpga_spl.itb with fit_fpga_spl.its in \u-boot-socfpga\board\altera\arria10-socdk

I recompiled U-Boot with #define DEBUG in include\configs\socfpga_common.h and found these error:

…
No configuration specified, trying default…
Found default configuration: ‘config-1’
FPGA: FPGA node count: 2
FPGA: fpga-periph-1
FPGA: fpga-core-1
FPGA: Start to program core bitstream …
FPGA: Data offset was found.
Can’t get ‘load’ property from FIT 0xffe24ec0, node: offset 248, name fpga-core-1 (FDT_ERR_NOTFOUND)
FPGA: No loadable was found.
FPGA: Using default DDR load address: 0x400 .
FPGA: External data: offset = 0x582d4, size = 0x1dcfb44.
blk_find_device: if_type=6, devnum=0: [email protected], 6, 0
…

Does anyone have any idea what the problem could be?

  • LFrin's avatar
    LFrin
    3 years ago

    Hi @aikeu,

    okay, now im sure: The Intel In-System Sources and Probes IP hinders the FPGA from starting normally after it has been correctly configured by SD-Card. Even the old Quartus-Project works without the ISSP-IP. Now it makes sense why the FPGA starts when a connection to the programmer is established via JTAG or similar.

    My workaround will be, that i only use FPGA Firmware without the debugging features (ISSP, SignalTap, ...) on the SD-Card and when i need this debugging features i will start the HPS with the ARMD DS debugger.

    Thanks for the help, my problem has been solved.

    Regards,

    LFrin

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  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi LFrin,


    Good that you managed to run a working example on on your side.

    May I know any new findings from your side after you tried to seperate the components build in your project?


    Thanks.

    Regards,

    Aik Eu


  • LFrin's avatar
    LFrin
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Hi @aikeu,

    Of course, I can keep you updated. I have successfully put the following components into operation without affecting the SD-Card startup:

    - Of course the Hard Processor System

    - PCI-Express Hard-IP

    - Nios V Soft-IP with I2C/GPIO/Timer/JTAG-Uart/Voltsense/Tempsense

    - Transceiver Native PHY (for SFP+-Fiber-Module)/Reset Controller/ATX PLL

    The only thing missing now is an "In-System Sources and Probes" IP, I think this IP could be the problem.

    Unfortunately I won't get to work on this project this week. But I will get back to you at the beginning of the next week.

    Thanks,

    Regards,

    LFrin

  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi LFrin,


    Thanks for your feedback. Looking forward to your new findings.


    Regards,

    Aik Eu


  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi LFrin,


    Do feedback to me once you got some update on this week.


    Thanks.

    Regards,

    Aik Eu


  • LFrin's avatar
    LFrin
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Hi @aikeu,

    my new Quartus project is now designed like the old one, except that I don't use an "In-System-Source-and-Probes" IP and a "Signal-Tap" instance. In the old project I used the ISSP-IP to reset the FPGA. It might be that the initial value is wrong when booting from SD card and the FPGA stays in reset.

    I believe one of these two instances is causing this problem. Tomorrow I will integrate both into my new project and then see if the error occurs.

    Regards, LFrin

    • LFrin's avatar
      LFrin
      Icon for Occasional Contributor rankOccasional Contributor
      3 years ago

      Hi @aikeu,

      okay, now im sure: The Intel In-System Sources and Probes IP hinders the FPGA from starting normally after it has been correctly configured by SD-Card. Even the old Quartus-Project works without the ISSP-IP. Now it makes sense why the FPGA starts when a connection to the programmer is established via JTAG or similar.

      My workaround will be, that i only use FPGA Firmware without the debugging features (ISSP, SignalTap, ...) on the SD-Card and when i need this debugging features i will start the HPS with the ARMD DS debugger.

      Thanks for the help, my problem has been solved.

      Regards,

      LFrin

  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi LFrin,


    Glad that the issue has been resolved and thanks for sharing with the workaround method through your troubleshooting process.

    I will close this thread for now and do consider open a new thread when there is further question.


    Thanks agian.

    Regards,

    Aik Eu