Arria 10 ASDATA Flash interface

Hello,
why should it not be possible? The method is just the same as using ASMI Parallel without dedicated AS interface, connecting asmi pins on the design top interface.

I found however, that ASMI parallel IP is well suited for similar purposes, with a few modifications like gating DCLK and possibly tri-stating asmi pins if concurrent devices are driving the flash in your design.

Regards,

Frank

When trying to assign the pins in Quartus, Quartus says the pins are unassignable.

Tried changing DATA0 in device and pin options, still get the same error in pin planner saying pin is unassignable.

As well, there are no options in device and pin options for DCLK or AS_DATA1/2/3.

Hi,

According to Arria 10 Pin Connection Guideline, it is not mentioned that the AS_DATA0/ASDO and AS_DATA[1:3] pins can be used as GPIO pins. It does not mention that these pins can be used after configuration.

"When you do not program the device in the AS configuration mode, the ASDO pin is not used. When you do not use this pin, leave the pin unconnected. "

A10 PCG: https://www.intel.com/content/www/us/en/docs/programmable/683814/current/optional-dual-purpose-configuration-pins.html

Thanks & Regards,

Xiaoyan

Hello,
I overlooked the point that with Arria 10 (also Cyclone 10 CX) AS pins are not dual purpose and can't be regularly accessed in user mode. Thanks for clarifying.

It's however possible to instantiate e.g. ASMI parallel with dedicated ASMI interface. It should allow to read and write AS configuration flash in user mode, isn't it?

Regards,
Frank

Hi,

What Frank (FvM) mentioned in the last reply is correct.

Configuration FLASH can be accessed during user mode. But some FPGA AS Configuration pins, including ASDATA, can not be accessed during user mode.

To access the AS configuration FLASH during user mode we can use certain IPs, such as ASMI Parallel II and Generic FLASH loader. User can also write their own user logic module for FLASH controlling.

About these IPs, we need to pay attention to the statements in IP user guide to make sure it works for you.

"The ASMI Parallel Intel FPGA IP core only supports the EPCS, EPCQ, EPCQ-L, and EPCQ-A devices.

The ASMI Parallel II Intel FPGA IP only supports the EPCQ, EPCQ-L, and EPCQ-A devices.

If you are using third-party flash devices, you must use the Generic Serial Flash Interface Intel FPGA IP."

Thanks & Regards,

Xiaoyan

Hello,
according to my experience, typical third-party configuration flash devices are suffciently compatible with EPCS/EPCQ and work well with ASMI Parallel IP. The old IP is my preference because if provides a leaner interface to a non-Avalon-MM design. Surely a matter of taste.

Regards,

Frank

Hi,

After some research and playing around I've managed to gain access to the pins in user mode using the Arria 10 primitives.

I am having issues trying to read/write the flash memory. The Micron device keeps returning all FF for every read of memory locations.

I can read device ID okay.

I can read flag status register okay.

I can read status register okay.

I can change between 4 byte address mode and 3 byte address mode and read back these flags from flag status register so I know I have some comms with the flash device and Arria 10.

When writing the flash this is the sequence I am using:
- Command code write enable.

- Read status register to check wr en latch bit set.

- Command code 4-byte page program with data sent to flash in this step being x"12"(cmd code) & x"0000_0000"(4-byte address) & x"0123_5678"(4 bytes of data). Using extended(normal) SPI mode, with DQ0 being SPI in and DQ1 being SPI out.

- Read status register to check wr en latch bit cleared and no error bits set.

- Read location in memory but data still x"FFFF_FFFF". Data sent to flash for read is x"13"(cmd code)& x"0000_0000"(4-byte address)& x"0000_0000"(clocks for read data return).

I have also tried these steps with an erase first, but seeing as the memory is already FF an erase should not be required and the same issue of FFFF persists?

I have also observed that sometimes the wr en latch bit is not able to be set with the wr en command unless I first read the flag status register. Is this normal?

I realise this might not be the correct forum for this as Micron flash issues might be outside of scope of Intel support but any help/suggestions will be greatly appreciated.