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Altera_Forum's avatar
Altera_Forum
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14 years ago

array support

Hi, is there a possibility to define an VHDL array so, that in an EPC3C55 the array uses the internal RAM cells. Actually the array uses only the logic elements. Thanks best Jo
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thank you Sokrates,

the hint was quiet good. But I have a problem. Let's tell you:

I have an external processor interface, where the array is filled with data. In my vhdl module I want to use this data for i.e. an arbitray generator. But when I try to read the data

(PhaseTime(15 downto 0) := unsigned(Data(Index+OFS_PHASE_Phasendauer+1));

the syntesis generates only logic modules and no ram.

best

Jo