Arial10 Power-Up Calibration Clock Question

Given your specific implementation - my understanding of how A10 GXBs work (with PCIe) is that both of the PCIe banks need to be connected to a host and properly calibrated in order for the 2x GXBs that are used for inter-FPGA communication can be properly calibrated. This is assuming that both PCIe Gen3x8 are using the Hard IP (HIP). Rules might be different if not using HIP, but I would guess that you went the route of HIP for this device. The use case that I have is using another piece of DisplayPort IP that has calibration logic built into it. I can't speak to whether you would expect de-rated performance on a link where you have control over PLL+reconfig+PHY and could possibly "trick" it into thinking that it's OK based on lack of calibration (not recommended).

I just wanted to point out that there are some interesting dependencies that need to be accounted for when using PCIe HIP that might or might not be connected.