Forum Discussion
ContributorArial10 Power-Up Calibration Clock Question
Hi @xytech
Calibration starts during configuration.
No timing sequence, the time for calibration to complete vary by device.
Based on experience, faster configuration time is needed if you are designing for open-system to meet the 100ms. For closed-system, you can adjust the PERST to allow more time.
Hope this helps.
New ContributorGiven your specific implementation - my understanding of how A10 GXBs work (with PCIe) is that both of the PCIe banks need to be connected to a host and properly calibrated in order for the 2x GXBs that are used for inter-FPGA communication can be properly calibrated. This is assuming that both PCIe Gen3x8 are using the Hard IP (HIP). Rules might be different if not using HIP, but I would guess that you went the route of HIP for this device. The use case that I have is using another piece of DisplayPort IP that has calibration logic built into it. I can't speak to whether you would expect de-rated performance on a link where you have control over PLL+reconfig+PHY and could possibly "trick" it into thinking that it's OK based on lack of calibration (not recommended).
I just wanted to point out that there are some interesting dependencies that need to be accounted for when using PCIe HIP that might or might not be connected.
xytechHi JCann,
We found solution for this pcie 100ms problem. In <ug01145_a10_pcie_avmm> doc, it clearly states that "Autonomous Mode" can satisfy pcie 100ms wake up time as long as user choose the specific hard pcie IP. this info is on section 12.2.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avmm.pdf
thanks again for help. good day.
