Forum Discussion
ContributorArial10 Power-Up Calibration Clock Question
Hi @xytech
Calibration starts during configuration.
No timing sequence, the time for calibration to complete vary by device.
Based on experience, faster configuration time is needed if you are designing for open-system to meet the 100ms. For closed-system, you can adjust the PERST to allow more time.
Hope this helps.
New ContributorWith an Arria 10 design at that density, I would recommend looking at CvP (configuration via protocol). My understanding is that this is meant to load the periphery of FPGA (including PCIe core) in order to satisfy the 100ms enumeration requirement. Then the "core" FPGA (rest of the logic) is loaded after the PCIe interface is safely up. Looks like datasheet calls out minimum config time for that device of >600ms when using AS (active serial) x4. Best case for FPP is slightly less than 100ms.
Regarding calibration, both clocks should be required (PCI_REFCLK and CLKUSR). CLKUSR toggles PreSICE state machine that runs the calibrations and you need the REFCLK for the PLLs. Keep in mind that in A10 devices, PCIe (w/ hard IP) are the first devices that calibrate and then cascade the CAL* status bits downstream to other GXBs on the chip. If you have a PCIe interface instantiated in your project that's not hooked up to anything (so not successfully calibrating), it will gate other GXBs from calibrating. Running into that right now with a design.
xytechHi JCann,
Thanks for reply. We use 2 GXB banks for PCIe GEN3.0 x8 linked to a Standard PC module. The rest 2 GXB banks are used for communication between two Arial 10 FPGAs.
Just to confirm I percept your second paragraph correctly, is following what you mean?
------After FPGA is powered up, among all GXBs, PCIe hard IP GXBs are firstly calibrated, and then certain CAL* status bits/signals are cascaded (delivered) downstream to other 2 GXBs for calibrating. If PCIe GXBs is not successfully calibrated, it will GATE(Prevent) other GXBs from calibrating, which means finally all GXB banks will not be calibrated successfully , and cannot function correctly. ------
Furthermore, as UG-01143 writes, “Transceivers include both analog and digital blocks that require calibration to compensate for process, voltage, and temperature (PVT) variations”
Just wondering, if it’s not calibrated successfully, how will transceivers behave? Will it become unable to work completely, or work with de-rated performance, such as lower speed rate, worse BER?
And if we enable datas compression funtion in Quartus to reduce bits stream file's size(typically reduce by 30%-55%), will the config time be reduced?
Thanks for helping!
