Forum Discussion
ContributorArial10 Power-Up Calibration Clock Question
Hi @xytech
Calibration starts during configuration.
No timing sequence, the time for calibration to complete vary by device.
Based on experience, faster configuration time is needed if you are designing for open-system to meet the 100ms. For closed-system, you can adjust the PERST to allow more time.
Hope this helps.
Frequent ContributorHi @xytech
Calibration starts during configuration.
No timing sequence, the time for calibration to complete vary by device.
Based on experience, faster configuration time is needed if you are designing for open-system to meet the 100ms. For closed-system, you can adjust the PERST to allow more time.
Hope this helps.
ContributorHi JwChin, thank you very much for patient reply.
As UG-01143 section 7.3 writes, PCIe links do not allow user recalibration. We have no choice. Only can do power up calibration.
OK, finally confirmed that Calibration starts during configuration and no specific timing, cal_busy indicates Calibration completes.
Yes, we do design OPEN-System. Root PCIe node is a standard x86 COMe module (compact PC module), and we cannot control when PERST# will be released.
Actually in our older product, we use Artix-7A200T FPGA of Xilinx, which DO NOT explicitly requires “transceiver Reference clock must be stable and free running BEFORE FPGA powered up for successful XCVR calib”(they do not need CLKUSR neither) , so our system are designed to power FPGA first, after detect its CONFIG_DONE signal released (pulled high), then we start PC module, this made sure PC can enumerate FPGA PCIe node. It worked fine.
Now it’s clear that this solution is NOT suitable for Intel A10. So we must change a fast enough configuration scheme to satisfy PCIe 100ms requirement. Hardware and/or Logic design need modifications inevitablely.
Thanks again for your kind help. Good day
