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Honored Contributor
Honored ContributorAre the LVDS terminations react on Pins in which no signal pass ?
Hi, I run simulation of cyclone 5 LVDS signal in Hyperlynx SI using IBIS model created by Quartus compilation. According to the Assignment Editor/PinPlanner the input termination on that pin...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- You can observe that Quartus doesn't place a LVDS input without a respective input port. Do you say, the termination isn't connected although the pin is defined as input port, but not driving actual logic? Which FPGA family? --- Quote End --- Yes, that's exactly what I meant. FPGA Family : Cyclone V GX C5 F27 Grade 7 Manufacturer Part Number - 5CGXFC5C6F27C7N.
