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Altera_Forum
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7 years ago

Are the LVDS terminations react on Pins in which no signal pass ?

Hi, I run simulation of cyclone 5 LVDS signal in Hyperlynx SI using IBIS model created by Quartus compilation. According to the Assignment Editor/PinPlanner the input termination on that pin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

You can observe that Quartus doesn't place a LVDS input without a respective input port. Do you say, the termination isn't connected although the pin is defined as input port, but not driving actual logic? Which FPGA family?