Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorAre the LVDS terminations react on Pins in which no signal pass ?
Hi, I run simulation of cyclone 5 LVDS signal in Hyperlynx SI using IBIS model created by Quartus compilation. According to the Assignment Editor/PinPlanner the input termination on that pin...
Altera_ForumHonored Contributor
Honored ContributorYou can observe that Quartus doesn't place a LVDS input without a respective input port. Do you say, the termination isn't connected although the pin is defined as input port, but not driving actual logic? Which FPGA family?
