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Honored Contributor
Honored ContributorAre Pll outputs in phase between different PLL when using the same reference clock
In the following scenario, If I have PLL A and PLL B driven from the same input reference clock (50MHz). Each PLL creates a 200MHz clock with no phase shift. The PLL is set in 'no compensati...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- 4) Could the PLLs get out of phase with each other if their async resets are released at different times? --- Quote End --- I would not count on the outputs of two independent PLLs to be in phase after simultaneous release of the async reset. When the async resets are released, each charge pump will start charging at slightly different rates. Remember that this is an analog circuit, and filter components will vary within tolerances. During this period, the oscillators are not locked to the final frequency, and certainly not to each other.
