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Altera_Forum
Honored Contributor
Honored ContributorAre Pll outputs in phase between different PLL when using the same reference clock
In the following scenario, If I have PLL A and PLL B driven from the same input reference clock (50MHz). Each PLL creates a 200MHz clock with no phase shift. The PLL is set in 'no compensati...
Altera_ForumHonored Contributor
Honored ContributorThanks for your replies
It seems like there will be a phase shift due to internal routing but they won't be out by nanoseconds. Timequest should analyse these paths and highlight them if they don't pass timing. If they pass then everything is ok. It is a dumbed down scenario for ease of explanation but it is a real issue of a more complex system with a bunch of constraints that has forced me down this line. I just wanted to make sure timequest was not hiding something from me. Josyb, Yes that is what would happen in this simple scheme ;-)
