Are outputs of PLL related all the time?

no.. thats not what i want to know.

All i want to know is that, how should i group the output of PLL during the timing contraint process.

For example:

set_clock_groups -asynchronous

-group {adc_clk

adcpll_output[0]

adcpll_output[1]}

-group {sys_clk

syspll_output[0]

adcpll_output[2]}

something like these... so my original question was, how should i group these pll clock if;

1)What if the output frequency is multiple of the input frequency ? would it be in different group or same group?

2)What if the output frequency is NOT multiple of the input frequency ? would it be in different group or same group?

3)What if the output frequency is phase shifted of the input frequency ? would it be in different group or same group?

4)What if the output frequency is phase shifted and multiple/non-multiple of the input frequency ? would it be in different group or same group?

Sorry for the confusion.

Regards,

Michael