Are outputs of PLL related all the time?

Indeed as long as PLL stays in lock then you shouldn't worry.

I don't see that jitter will vary practically with your conditions for a given PLL but the meaning of "locked" is arbitrary and depends on how much jitter is accepted as "locked"

The loop is analogue and is based on phase error detection between internal osc frequency Fosc,and generated frequency Fout, followed by damping through loop filter then applying erorr in reverse on oscillator.

The error will never become zero but will "oscillate" up and down with possible variation over time/temperature.

Then jitter = amplitude of error oscillation.

Jitter may not be same at all cases of chosen frequency values but can be forced for better by modifying loop filter.