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Unfortunately, I am relatively new to VHDL and Altera Quartus, so I couldn't really comprehend your statement above...
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My answer isn't particularly related to VHDL nor Quartus. It's a general statement about mathematical operations. Instead of trying to explain the matter further, let me say: Get you a pencil and paper (or may be a pocket calculator for convenience) and try to figure it out.
To turn your above code into legal VHDL and also perform the apparently intended operation in all cases, you would change it like this:
FOR i IN 31 DOWNTO 15 LOOP
IF datain(i) /= '0' OR i =15 THEN
out_msb <= datain(i DOWNTO (i-15)); -->line 41
EXIT;
END IF;
END LOOP;
It takes not less than 185 Cyclone III logic cells, but gets a result in one cycle. By designing a sequential shift, you can considerably reduce the effort, but have to wait up to 16 cycles.
You'll find a similar logic in a floating pointer normalizer. In addition, you would output the actual shift that's used for the exponent. In fixed point arithmethic, you try to avoid variable scaling, saturation logic, as mentioned above, may be necessary however.
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