Are only MSBs outputted if bits are restricted?

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Unfortunately, I am relatively new to VHDL and Altera Quartus, so I couldn't really comprehend your statement above...

I was actually coding something along these lines:

BEGIN

PROCESS (clock)

BEGIN

IF (clock = '1') THEN

FOR i IN 31 DOWNTO 0 LOOP

IF datain(i) /= '0' THEN

out_msb <= datain(i DOWNTO (i-15)); -->line 41

END IF;

END LOOP;

END IF;

END PROCESS;

END rtl;

But compiling this gives me an error:

"error (10453): vhdl error at msb_output.vhd(41): right bound (-1) of slice must belong to range (31 downto 0) of corresponding object"

What I was trying to do is loop until I get the first '1' from the left, then take the 16-bits starting from the first '1' as my 16-MSB output.

Help and guidance will be highly appreciated.

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In HDL, for loops are unrolled at synthesis time - loops do not exist on hardware. Whats happening here is that it's getting to i = 14 and then it tries to take the slice 14 downto -1. What the synthesisor is creating is a 32 to 1 mux with all the different inputs (31 downto 16), (30 downto 15) etc available, and then all the bits are put through logic gates to create select lines that select the appropriate 16 bit word. But as you've seen, your code tries to create and input to this MUX with an invalid range.