Are only MSBs outputted if bits are restricted?

Unfortunately, I am relatively new to VHDL and Altera Quartus, so I couldn't really comprehend your statement above...

I was actually coding something along these lines:

BEGIN

PROCESS (clock)

BEGIN

IF (clock = '1') THEN

FOR i IN 31 DOWNTO 0 LOOP

IF datain(i) /= '0' THEN

out_msb <= datain(i DOWNTO (i-15)); -->line 41

END IF;

END LOOP;

END IF;

END PROCESS;

END rtl;

But compiling this gives me an error:

"error (10453): vhdl error at msb_output.vhd(41): right bound (-1) of slice must belong to range (31 downto 0) of corresponding object"

What I was trying to do is loop until I get the first '1' from the left, then take the 16-bits starting from the first '1' as my 16-MSB output.

Help and guidance will be highly appreciated.