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Honored ContributorAppropriate ADC for educational project?
Hello folks!
I'm a student of 'Network Systems and Data Communications' department in Greece and am doing my final project/dissertation right now in Leiria, Portugal at Electrical Engineering department. Because the subject is kind of complex, I'm going to introduce to you only the part on which I'd like to set my specific question. I want to implement a small device/circuit which will be inputted some analog voice commands from a normal electret mic. Till now I'm not clear about what pre-amp/op-amp I should use, but I believe I'll figure this out. The implemented circuit will be interfaced onto a Pluto-II (Cyclone-I) FPGA board, probably SPI/i2c will fit the best. I've read a lot about ADC's appropriate for voice/audio systems, and I suggest that an Σ-Δ (sigma-delta) ADC will be good for me, in combination of a simple low-pass anti-aliasing filter consisting of a resistor and a capacitor in parallel before the ADC. Actually, regarding the Σ-Δ ADC I still have no clear image if it is a linear or logarithmic ADC, cause as far as I know, it should be a logarithmic one for audio sampling, isn't it? Considering a specific topic of your forum and obvious knowledge you people got, I thought that maybe you could suggest to me any appropriate market ADC for my purpose. Thank you! Sincerely, David32 Replies
Altera_ForumDear Amilcar,
This LPF that you sent me on the verilog code. What values has implement on the LPF? and which is the Cut-off Frequency? If I want change the Cut-off frequency i will change these signals? logic signed [3*utils::MinBits(DECIMATION-1)+1:0] DELTA1 = 1'd0; logic signed [3*utils::MinBits(DECIMATION-1)+1:0] CN1, CN2 = 1'd0; logic signed [3*utils::MinBits(DECIMATION-1)+1:0] CN3, CN4; logic signed [3*utils::MinBits(DECIMATION-1)+1:0] DN0, DN1, DN3, DN5 = 1'd0; thank you again.- Altera_Forum
I think amilcar gave me the Verilog code of both Decimation and LPF if i am not misstaken!!!!
- Altera_Forum
I am sorry, i meant how many bits will be the Word - o_result if the Decimation will be 512?
It will be 16bits? Thank you!!! - Altera_Forum
Which MSB ?
- Altera_Forum
Yep you helped me a lot,
One more thing.. How many bits are the MSB? It depends on the Decimation ratio? - Altera_Forum
On the top of the file you can see the function that converts Decimation in EffectiveNumberOfBits (ENOB) .
By changing the decimation you get different bitwidths. If decimation = 1 you get one word per clk cycle (bad performace because the word is 1 bit) If i.e. decimation = 32 you get one word every 32th clk cycle. Hope this helps. - Altera_Forum
Dear Amilcar,
On the Verilog Code tou sent to David, at the Declaration, --- Quote Start --- input wire clk, // the main FPGA clk (its faster than the ADS1204 clk) input wire reset, // async reset input wire i_ds_clk_out, // the ADS1204 clk (derived from the main clk) input wire i_ds_out, // DS modulated output bit output reg signed [ADS1204::ENOB(DECIMATION)-0:0] o_result, // one extra bit for the sign output reg o_valid = 1'b0); // the result is new and valid --- Quote End --- In our application we want to encapsulate on the payload of UDP packets, so we will fill a buffer with the words from the ADC, 1. the " o_result" contains a word of how many bits? and 2. on how many clock cycles i will have one word? Also i want more than 12bits resolution for this audio application so what Decimation M number i will use? Sorry for asking all these but im Still confused!!! Thank you again!!!! Greetings From Beautiful Leiria!!!! - Altera_Forum
I recomended the ADS1202 because you can trade-off resolution with data-rate, and it has the nice effect of shaping the SNR by pushing noise into the higher frequencies.
BUT..... there night be others out there that are even better for audio applications. - Altera_Forum
1. Basically, yes. With the questioned resolution, not for a CD audio quality.
2. A good explanation of decimation and other basic topics of signal processing is in U. Meyer-Baese, digital signal processing with fpga. It's often refering to Altera tools and FPGA. And the classical paper of the CIC inventor Hogenauer, EB, "An Economical Class of Digital Filters for Decimation and Interpolation," IEEE Transactions on Acoustics, Speech and Signal Processing, ASSP-29(2): pp. 155-162, 1981 3. The most versatile audio converter covering the range from low rate to CD audio would be a programmable codec as utilized in many Altera and Terasic Dev Kits. It already includes decimation with an appropriate steep filter and outputs a serial audio data stream. - Altera_Forum
hmm ok, i need for my project an audio AD converter and you told my friend refugee that this ads1202 it can work for our purpose because it is a Sigma-Delta AD.
1.Can we use it for this application? 2.I have seen the VHDL code but i can understand it very good, can i find a book about that? 3.Is there anyother ADS which is better for Audio Convertion? Thank you very much for your time!!! We are realy appreciate your help!!
