Appropriate ADC for educational project?

Dear Amilcar,

On the Verilog Code tou sent to David,

at the Declaration,

--- Quote Start ---

input wire clk, // the main FPGA clk (its faster than the ADS1204 clk)

input wire reset, // async reset

input wire i_ds_clk_out, // the ADS1204 clk (derived from the main clk)

input wire i_ds_out, // DS modulated output bit

output reg signed [ADS1204::ENOB(DECIMATION)-0:0] o_result, // one extra bit for the sign

output reg o_valid = 1'b0); // the result is new and valid

--- Quote End ---

In our application we want to encapsulate on the payload of UDP packets,

so we will fill a buffer with the words from the ADC,

1. the " o_result" contains a word of how many bits? and

2. on how many clock cycles i will have one word?

Also i want more than 12bits resolution for this audio application so what Decimation M number i will use?

Sorry for asking all these but im Still confused!!!

Thank you again!!!! Greetings From Beautiful Leiria!!!!