Application of SSTL-18 class1 on communication between FPGA&DDR2

Wonder if Altera Applicatio Note (AN328) would help you on this ...

http://www.altera.com/technology/memory/devices/stratix2-2gx/mem-stratix2-2gx.html

I found below msg in that application notes:

On the FPGA side, Altera recommends the Series 25 Ohm without Calibration

OCT setting for bi-directional signals (such as DQ and DQS) and the Series

50 Ohm without Calibration OCT setting for unidirectional output signals to the

memory (such as DM and address/command). If there are multiple loads on

certain FPGA output pins (for example, when the address bus is driven to

multiple memory devices on a DIMM), you may prefer to use the maximum

drive strength setting over the series OCT setting. Note that when using the

OCT feature on the FPGA, the programmable drive strength feature is

unavailable.

Looks like you need to add series resistors on your signal traces.

The SSTL class 2 terminations scheme actually involves termination resistors at the FPGA and the memory side. See Altera AN408 figure 6 for reference. This would be a clear way to avoid the said unsymmetrical termination problem with bidirectional signals. Another option is dynamic OCT at the FPGA side, available since Stratix III.

Unfortunately, you most likely can't place termination resistors at both sides due to layout restrictions. But then, SSTL termination can't be more than a compromise.