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Altera_Forum
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16 years ago

Application of SSTL-18 class1 on communication between FPGA&DDR2

Now I am design my development kit , the FPGA I am using is Stratix 2'S device EP2S180F1020C5N , I will use DDR2 soDIMM on my development . So , according to the Handbook , I must use the SSTL-18 cl...
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Altera_Forum
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16 years ago

The SSTL class 2 terminations scheme actually involves termination resistors at the FPGA and the memory side. See Altera AN408 figure 6 for reference. This would be a clear way to avoid the said unsymmetrical termination problem with bidirectional signals. Another option is dynamic OCT at the FPGA side, available since Stratix III.

Unfortunately, you most likely can't place termination resistors at both sides due to layout restrictions. But then, SSTL termination can't be more than a compromise.