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Altera_Forum
Honored Contributor
19 years agoApparent Reset Glitch on Synchronous Reset
While running SW tests, at random times it looks like all my internal registers are getting cleared to their reset values. This is true for both registers and SOPC modules. Depending on the SW I ru...
Altera_Forum
Honored Contributor
19 years agotry put the reset signal as a clock to a TFF with T=1. Monitor Q. This should capture and enlarge any gliches, making it easier to see. Remember these glitches may be sub ns, never making it to a phyical pin, let alone a scope probe but still being able to wreck hawock a reset.