Forum Discussion
Altera_Forum
Honored Contributor
15 years ago --- Quote Start --- Thanks Thomas. The failing paths are on the heavily loaded global clocks nets (155 and 311). I think one problem is the device is running out of memory resources and then start chewing up LABs. Its not clear to me what the algorithm is for selecting memory to move to LABs. After reviewing some of the results, I think it may have made bad choices. For now we are going down the Incremental compile path and inserting pipeline stages where needed. This seems like it will work if we dont run out of space. BTW, do you know of anyone who has tried the "Team Based Flow". We are also looking at that. So far the auto generated makefiles seem all screwed up but we can fix that. I can build a partition that takes up 10 percent of the design in 20 minutes. I can do 10 jobs in parallel for my 10 partitions. Then, in theory, should just have a short compile to route and connect things. Should be done in 2 hours instead of 24; at least that is how it is advertised.... --- Quote End --- Hi, some thoughts about the team based flow .... In my point of view it would be not a good decision to use a "team based flow" as long a your device utilization is so high. Using partitons means that the design could not optimized as good as before, because the IF of the partitions will be preserved. No optimization across partitions took place. Next point is that it is recommended to use registered input and output at the partition borders, in order to prevent timing issues between partitions. This will eat up some resources again. For the partitions you have to define LogicLock regions. That means you have to assign resources to the partitions. You can not fill up the Logiclock region 100%, you will waste some resources (especially memory could be a problem. To get the full advantage of the flow you have to use the preserving level "Placement & Routing". I assume you will run all your partitions separat and import them in your main projekt. By doing this you could run into some problems, especially with the clock ctrl blocks. I'm not sure that Quartus is able to detect that two partitions use the same clock and the clock ctrl blocks ( they are part of the placement and routing ) could be merged. kind regards GPK