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Just some brainstorming (I mostly use Cyclone, so maybe something does not really apply for Stratix):
- Try to reduce the number of used logic (maybe, with 90% it would fit like a charm), either by changing the RTL-code and / or by changing compiler-options (e.g. maximum register-packing, optimze for area instead of optimze for speed)
- You mentioned 200 clocks. The clocks with failing paths, are they using global clocks or non-global routing-resources? If they use non-global, try to reduce the number of clock-domains so that only global resources are needed (this would also free routing-resources for normal routing).
To get an impression: What frequencies do you want to achieve, what is your "typical" slack in the moment?
Thomas
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Thanks Thomas. The failing paths are on the heavily loaded global clocks nets (155 and 311). I think one problem is the device is running out of memory resources and then start chewing up LABs. Its not clear to me what the algorithm is for selecting memory to move to LABs. After reviewing some of the results, I think it may have made bad choices.
For now we are going down the Incremental compile path and inserting pipeline stages where needed. This seems like it will work if we dont run out of space.
BTW, do you know of anyone who has tried the "Team Based Flow". We are also looking at that. So far the auto generated makefiles seem all screwed up but we can fix that. I can build a partition that takes up 10 percent of the design in 20 minutes. I can do 10 jobs in parallel for my 10 partitions. Then, in theory, should just have a short compile to route and connect things. Should be done in 2 hours instead of 24; at least that is how it is advertised....
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