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1/ we had most of the design blocks running fine in 90 nm (stratix ii gx). the problem is mostly ic delay.
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I had the same problem in a StratixII GX project (EP2SGX60F1152C3). Our GX logic uses a lot of M4K, about 2/3 of them and apparently that makes the signals cross the device from left to right and back.
We reduced the logic by using a 192 bit datasize in stead of 216 bit, this reduced the utilization to 78% (coming from 100+), but then we had to increase the speed to 175 MHz. The failing paths had IC delays of 75+ %. I cured the problem by adding pipeline registers between a few blocks. This allows the router to cross the device in two steps and give it some headroom for others.
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