another question

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity Ttrigger2 is

port(t,clk:in std_logic;

q:buffer std_logic);

end Ttrigger2;

architecture b of Ttrigger2 is

begin

signal qq:std_logic;

process(clk)

begin

if t='1' then qq<=not qq;

else qq<=qq;

end if;

end process;

q<=qq;

end b;

Error (10500): VHDL syntax error at Ttrigger2.vhd(10) near text "signal"; expecting "end", or "(", or an identifier ("signal" is a reserved keyword), or a concurrent statement