Another question about component instantiation

Hi,

I have a query about the component instantiation. The structure of my code is as follows:

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

USE ieee.std_logic_unsigned.all;

entity main is

port

(

clk : in std_logic;

port1: in std_logic;

port2: out std_logic;

port3: in std_logic;

port4: out std_logic

);

end main;

architecture main_behavior of main is

component componet1 is

port

(clkin : in std_logic;

a: in std_logic;

b: out std_logic

);

end component;

component component2 is

port

( clkin : in std_logic;

c: in std_logic;

d: out std_logic

);

end component;

begin

first: abc port map

(

clkin =>clk,

a=> port1,

b=> port2

);

second: def port map

(

clkin =>clk,

c=> port3,

d=> port4

);

end main_behavior;

In the code structure above, I have both componet1 and component2 who triggers based on the same clock but they have different input and output ports.

However, when I do the simulation, the result is funny: If I have either component1 or component2 only in the code, the simulation is good. but if I use both component1 and compnent2, one component's result is wierd while the other one is good. The weird waveform seems to behave like fighting with itself after some clock cycles periodically.

:cool:

Can anybody give me some advice on this?

THANK YOU SO MUCH FOR YOUR TIME IN ADVANCE!!!!