Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Another question about component instantiation

Hi, I have a query about the component instantiation. The structure of my code is as follows: LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_l...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Your top design doesn't contain any logic. It's just wiring the components. Thus it's effectively meaningless for the the timing behaviour. The reported behaviour sounds strange indeed, the reason should be searched either in the component definition or in the particulur simulation setup. If the simulation waveform involves timing violations, the result may depend however on minimal routing delay differences between your simulation designs.