Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributoraltsyncram in simple dual-port mode
Hi, the altsyncram in simple dual-port mode does not seem to work correctly. It appears to have some internal pipelining on the data and address inputs relative to the wren and even each other.
Also, the modelsim model seems to work slightly differently than the actual FPGA-based instantiation (shown with Signal Tap). Any insights into the use of this megafunction in the Stratix III? Thank you for any help! Shayle12 Replies
Altera_Forum--- Quote Start --- the modelsim model seems to work slightly differently than the actual FPGA-based instantiation (shown with Signal Tap). --- Quote End --- Post your testbench, the testbench waveforms and your SignalTapII waveforms. I've never had any issues with Modelsim vs SignalTap with the altsyncram component (except for the time I used a newer version of Modelsim-SE, rather than the Modelsim-ASE version shipped with Quartus). Though I've only ever used it in single-port or dual-port mode. Perhaps simple dual-port has an issue. You could try it in dual-port mode and see if that changes the results. Cheers, Dave- Altera_Forum
In any ram you may have options of registering the input, address, output. Moreover the clock edge used may not always be the rising edge. This may be behind what you observed though you haven't specified what is wrong.
