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Altera_Forum
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14 years ago

altsyncram in simple dual-port mode

Hi, the altsyncram in simple dual-port mode does not seem to work correctly. It appears to have some internal pipelining on the data and address inputs relative to the wren and even each other. ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Hi Dave,

Yes, good advice. All very true.

I will do that later, when I get back to Verilog. For now, I am using AHDL and letting Quartus generate the netlist.

When I get a chance, I will follow your recommendation.

Thanks,

Shayle